Methods for Manufacturing Arrays for CMOS Imagers

ABSTRACT

Methods of fabricating complementary metal-oxide-semiconductor (CMOS) imagers for backside illumination are disclosed. In one embodiment, the method may include forming at a front side of a substrate a plurality of high aspect ratio trenches having a predetermined trench depth, and forming at the front side of the substrate a plurality of photodiodes, where each photodiode is adjacent at least one trench. The method may further include forming an oxide layer on inner walls of each trench, removing the oxide layer, filling each trench with a highly doped material, and thinning the substrate from a back side opposite the front side to a predetermined final substrate thickness. In some embodiments, the substrate may have a predetermined doping profile, such as a graded doping profile, that provides a built-in electric field suitable to guide the flow of photogenerated minority carriers towards the front side.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a non-provisional of U.S. Provisional PatentApplication Ser. No. 61/369,846 filed Aug. 2, 2010, the contents ofwhich are hereby incorporated in their entirety.

BACKGROUND

Disclosed are methods of fabricating a photodetector array or pixelarray for manufacturing complementary metal-oxide-semiconductor (CMOS)imagers, and to methods of fabricating CMOS imagers for backsideillumination.

Backside illuminated CMOS imagers are known to have an excellent quantumefficiency that can compete with backside illuminated charge-coupleddevices (CCDs), as for example demonstrated by K. De Munck et al., in“High performance hybrid and monolithic backside thinned CMOS imagersrealized using a new integration process”, IEEE International ElectronDevices Meeting, San Francisco, US. December 2006, p 139-142. Thisexcellent quantum efficiency was achieved by providing an epitaxiallayer with a graded doping profile (where the graded doping profileprovided a built-in electric field that guides the flow ofphotogenerated electrons (minority carriers) towards the depletionregion at the front side), and performing backside Boron implantationand subsequent laser annealing for good backside passivation. However,it was noticed that the cross-talk was large in these backsideilluminated CMOS imagers or sensors. About 88% overall signal leakagewas observed.

Two approaches of fabricating thinned backside illuminated CMOS imagersexist: a monolithic approach and a hybrid approach. In a monolithicapproach, a photodetector array or pixel array and the correspondingreadout integrated circuit (ROIC) are produced in a same substrate, andboth the pixel array and the ROIC are thinned. In a hybrid approach, thephotodetector array is produced separately and hybridly integrated onthe ROIC, such that only the photodetector array needs to be thinned.Each pixel of the array is connected to the ROIC by a metal bump, suchas an indium bump.

To reduce the crosstalk between pixels (photodetectors) caused by thediffusion of photogenerated carriers between the pixels of backsideilluminated imagers, a structure comprising deep trenches filled withhighly doped polysilicon between the photodetectors has been proposed(K. Minoglou et al, “Reduction of electrical crosstalk in hybridbackside illuminated CMOS imagers using deep trench isolation”, IITCConf. San Francisco, June 2008, pp. 139-142). However, it was observedthat the presence of the trenches negatively affects the quantumefficiency of the imagers. This is illustrated in FIG. 3, showing themeasured quantum efficiency for a device without trenches (solid line)and for a device with trenches (dashed line). This difference in quantumefficiency is much larger than would be expected based on the lower fillfactor due to the presence of trenches (leading to about 10% loss inquantum efficiency).

SUMMARY

Disclosed are alternative methods for fabricating CMOS imagers. Someembodiments are for backside illumination, wherein the imagers have verylow electrical crosstalk (e.g., close to zero crosstalk) betweenneighboring pixels as well as very good quantum efficiency (e.g., closeto 100% internal quantum efficiency) in a wavelength range of interest(e.g., in a wavelength range between 400 nm and 900 nm).

Particular aspects are set out in the accompanying independent anddependent claims. Features from the dependent claims may be combinedwith features of the independent claims as appropriate and not merely asexplicitly set out in the claims. Any features may be disclaimed fromany of the aspects.

In one aspect, a method of fabricating a photodetector array or a pixelarray for a CMOS imager is disclosed. The method comprises forming in afront side of a substrate a plurality of high aspect ratio trencheshaving a predetermined trench depth. The method further comprisesforming a plurality of photodiodes at the front side of the substrate,where each photodiode is adjacent at least one trench. The methodfurther comprises forming an oxide layer on inner walls of each trenchin the plurality of trenches, removing the oxide layer, filling eachtrench in the plurality of trenches with a highly doped material, andthinning the substrate from a back side opposite the front side to apredetermined thickness.

In some embodiments the oxidation step and the subsequent removal of theoxide layer from the walls of the plurality of trenches substantiallyremoves defects, residues and impurities from the sidewalls of thetrenches, leading to a reduction of charge carrier recombination at thetrench sidewalls.

The cleaning of the sidewalls by removal of the oxide, can remove orsubstantially reduce any diffusion barrier (such as for example a nativeoxide) from the trench sidewalls, thus allowing a good out-diffusion ofdopants from the highly doped polysilicon filling the trenches into thephotosensitive layer. This can thereby create a built-in electric fieldfurther reducing charge carrier recombination at the trench sidewalls.

In some embodiments, the substrate may be a substrate with apredetermined doping profile, such as a graded doping profile providinga built-in electric field that guides the flow of photogeneratedminority carriers towards the front side. This can for example beobtained by epitaxial growth of a silicon layer with the predetermineddoping profile on a sacrificial substrate (e.g., a substrate that is atleast partially removed in a later stage of the process).

In some embodiments, the high aspect ratio trenches may have a depth atleast ten times their width.

In some embodiments, the predetermined trench depth is at least as largeas the predetermined final substrate thickness, such that in a finisheddevice the plurality of high aspect ratio trenches extends through thethinned substrate. However, the present disclosure is not limitedthereto and the predetermined trench depth can be smaller than thepredetermined final substrate thickness.

A method according to the present disclosure can advantageously be usedfor fabricating CMOS imagers for backside illumination.

For purposes of summarizing the disclosure and the advantages achievedover the prior art, certain objects and advantages of the disclosurehave been described herein above. Of course, it is to be understood thatnot necessarily all such objects or advantages may be achieved inaccordance with any particular embodiment of the disclosure. Thus, forexample, those skilled in the art will recognize that the disclosure maybe embodied or carried out in a manner that achieves or optimizes oneadvantage or group of advantages as taught herein without necessarilyachieving other objects or advantages as may be taught or suggestedherein. Further, it is understood that this summary is merely an exampleand is not intended to limit the scope of the disclosure as claimed. Thedisclosure, both as to organization and method of operation, togetherwith features and advantages thereof, may best be understood byreference to the following detailed description when read in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows a cross section of a CMOS imager, showing asingle pixel with trenches surrounding the pixel.

FIGS. 2A-F schematically illustrate process steps of a method inaccordance with an embodiment.

FIG. 3 shows the measured quantum efficiency of a 1000×1000 CMOS imagerwithout trenches and a 1000×1000 CMOS imager with trenches.

FIGS. 4A-B shows a schematic cross section of a p+ polysilicon filledtrench with a thin barrier layer (FIG. 4A) and the simulated effect ofthe barrier layer thickness on the dopant distribution profile in thesilicon substrate (FIG. 4B).

FIG. 5 shows the results of quantum efficiency simulations for thickbackside illuminated CMOS imagers wherein the pixels are separated bytrenches of different quality.

FIG. 6 shows the results of quantum efficiency simulations for thickfrontside and backside illuminated imagers wherein the pixels areseparated by trenches of different quality.

FIG. 7 shows measured and simulated quantum efficiency curves as afunction of wavelength for non-trenched test diodes and for trenchedtest diodes fabricated according to a method of the present disclosure.

FIG. 8 shows measured and simulated quantum efficiency curves as afunction of wavelength for non-trenched test diodes and for trenchedtest diodes fabricated according to a prior art method.

FIG. 9 illustrates a measurement setup used for performing quantumefficiency measurements of photodiodes.

In the drawings, the same reference signs typically refer to the same oranalogous elements, unless context dictates otherwise.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are setforth in order to provide a thorough understanding of the disclosure andhow it may be practiced in particular embodiments. However, it will beunderstood that the present disclosure may be practiced without thesespecific details. In other instances, well-known methods, procedures andtechniques have not been described in detail, so as not to obscure thepresent disclosure. While the present disclosure will be described withrespect to particular embodiments and with reference to certaindrawings, the disclosure is not limited hereto. The drawings includedand described herein are schematic and are not limiting the scope of thedisclosure. It is also noted that in the drawings, the size of someelements may be exaggerated and, therefore, not drawn to scale forillustrative purposes.

Furthermore, the terms first, second, third and the like in thedescription and in the claims, are used for distinguishing betweensimilar elements and not necessarily for describing a sequence, eithertemporally, spatially, in ranking or in any other manner. It is to beunderstood that the terms so used are interchangeable under appropriatecircumstances and that the embodiments of the disclosure describedherein are capable of operation in other sequences than described orillustrated herein.

Moreover, the terms top, bottom, over, under and the like in thedescription and the claims are used for descriptive purposes and notnecessarily for describing relative positions. It is to be understoodthat the terms so used are interchangeable under appropriatecircumstances and that the embodiments of the disclosure describedherein are capable of operation in other orientations than described orillustrated herein.

It is to be noticed that the term “comprising”, used in the claims,should not be interpreted as being restricted to the means listedthereafter; it does not exclude other elements or steps. It is thus tobe interpreted as specifying the presence of the stated features,integers, steps or components as referred to, but does not preclude thepresence or addition of one or more other features, integers, steps orcomponents, or groups thereof. Thus, the scope of the expression “adevice comprising means A and B” should not be limited to devicesconsisting only of components A and B.

In the context of the present disclosure, the front side of a substrateor of an imager is the side of the substrate or imager where thephotodiodes are provided. The back side or rear side of a substrate orimager is the side opposite to the front side.

In one aspect, a method of fabricating a photodetector array or a pixelarray for a CMOS imager is disclosed. The method comprises forming in afront side of a substrate a plurality of high aspect ratio trencheshaving a predetermined trench depth. The method further comprisesforming a plurality of photodiodes at the front side of the substrate,where each photodiode is adjacent at least one trench. The methodfurther comprises forming an oxide layer on inner walls of each trenchin the plurality of trenches, removing the oxide layer, filling eachtrench in the plurality of trenches with a highly doped material, andthinning the substrate from a back side opposite the front side to apredetermined thickness.

The disclosed method can advantageously be used for fabricating CMOSimagers for backside illumination.

In some embodiments, the substrate may have a graded doping profileproviding a built-in electric field guiding the flow of photogeneratedminority carriers towards the front side. Therefore, in someembodiments, the substrate may comprise a sacrificial substrate on whichan epitaxial layer is grown having a graded doping profile. Thinning thesubstrate from the back side can comprise completely removing thesacrificial substrate or it can comprise partially removing thesacrificial substrate.

The predetermined final substrate thickness of a CMOS imager fabricatedaccording to an embodiment of the disclosed method can, for example, bein the range between 5 micrometer and 50 micrometer, for example between10 micrometer and 30 micrometer. However, the disclosed method is notlimited thereto and the predetermined final substrate thickness can alsobe outside these ranges.

In some embodiments, the predetermined trench depth is at least as largeas the predetermined final substrate thickness, such that in a finisheddevice the plurality of high aspect ratio trenches completely extendsthrough the thinned substrate. However, the disclosed method is notlimited thereto and the predetermined trench depth can be smaller thanthe predetermined final substrate thickness.

Although the disclosed method is further described for embodimentswherein the substrate is a p-type silicon substrate, wherein photodiodesare formed by providing an n-type region (e.g., an n-well), and whereinthe highly doped polysilicon is p⁺ type silicon, the disclosed method isnot limited thereto. For example, the substrate can be an n-typesubstrate wherein photodiodes are formed by providing a p-type region(e.g., a p-well) and wherein the highly doped polysilicon is n⁺ typesilicon.

FIG. 1 schematically shows a cross section of a CMOS imager,illustrating a single photodiode or pixel with trenches surrounding thephotodiode. In the example shown, a photodiode is formed between ann-type well 20 and a p-type substrate 10. The p-type substrate 10 mayhave a graded doping concentration providing a built-in electric fieldguiding the flow of photo-generated electrons towards the front side.The substrate doping concentration can, for example, have a profile witha continuous slope resulting in a continuous electric field.Alternatively, the substrate doping concentration can, for example, havea “staircase” profile, meaning that the doping concentration decreasesstep-wise from the back side towards the front side. However, thedisclosed method is not limited thereto and other suitable dopingprofiles providing a built-in electric field guiding the flow ofphoto-generated electrons towards the front side can be used.

High aspect ratio trenches 30 (e.g., 1 micrometer wide and 30 to 50micrometers deep) filled with highly doped (p⁺) polysilicon 32 areprovided. The doping level of the p⁺ polysilicon 32 can, for example, beon the order of 10²⁰ cm⁻³ to 10²¹ cm⁻³, thus providing a lateral driftfield between pixels after diffusion into the substrate. Such a lateraldrift field counteracts diffusion of photogenerated charge carriersbetween pixels and thus limits electrical crosstalk between pixels. Atthe front side of the imager, a first electrical contact 11 to thep-type substrate 10 and a second electrical contact 21 to the n-well 20are provided, as well as a dielectric layer 40.

The cross section shown in FIG. 1 illustrates an example of a structurethat can advantageously be fabricated using an embodiment of thedisclosed method. However, the disclosed method can also be used forfabricating other structures comprising trenches.

FIG. 2 illustrates process steps of an embodiment of the disclosedmethod, as can be used for fabricating the structure shown in FIG. 1.The trenches 30 may be provided at the beginning of the process flow, atthe front side 1 of a p-type substrate 10, as shown in FIG. 2A. They canbe formed by a Deep-Reactive Ion Etching (DRIE) step, using, forexample, a photoresist and tetraethoxysilane (TEOS) as masks for theetching step. The trenches 30 may be, for example, about 1 micrometerwide and up to 50 micrometer deep. However, the disclosed method is notlimited thereto and larger or smaller trenches can be formed.

In some embodiments of the method, after etching the high aspect ratiotrenches, an oxidation step is performed, thereby forming an oxide layer31 at least on the sidewalls of the trenches, as shown in FIG. 2B. Theoxidation can, for example, comprise in-situ steam generated (ISSG)oxidation, at, for example, a temperature in the range between 850° C.and 1100° C. Alternatively, the oxidation can comprise wet oxidation ina H₂/O₂ ambient at, for example, a temperature in the range between 650°C. and 1050° C. Other methods that may be used for performing theoxidation step are dry oxidation in an O₂ ambient or Rapid Thermaloxidation, or any other suitable method known by a person skilled in theart. The thickness of the oxide layer 31 may be in the range between 3nm and 50 nm, or in the range between 10 nm and 30 nm. However, thedisclosed method is not limited thereto and other oxide thicknesses canbe used.

In a next step, the oxide layer 31 is removed at least from thesidewalls of the trenches 30, as shown in FIG. 2C. In some embodiments,the oxide layer 31 may be removed by wet etching. After removing theoxide layer, the trenches are filled with heavily doped (p⁺) polysilicon32, followed by chemical mechanical polishing (CMP) of the excesspolysilicon at the silicon surface. A cross section of the resultingstructure is shown in FIG. 2D.

In some embodiments, after removing the oxide layer, optionally a verythin oxide layer (e.g., with a thickness 1 nm to 2 nm) can be grown onthe sidewalls of the trenches before filling the trenches with heavilydoped polysilicon. Such a very thin controlled oxide layer can act as abarrier layer and limit or avoid excessive out-diffusion of dopants fromthe heavily doped polysilicon filling the trenches into the substrate,while allowing sufficient diffusion (as illustrated in FIG. 4B) topassivate the sidewall surface states. Excessive out-diffusion couldreduce the fill factor of the imager because the dopants can work asdefects.

After trench filling, photodiodes (and optionally other devices) areformed at the front side 1. This may involve several process steps, suchas active region definition, etching, implantations, silicidation ofcontact areas, metallization, passivation, etc. FIG. 2E shows a crosssection after photodiode formation, illustrating an n-type well 20forming the photodiode p-n junction with the p-type substrate 10, afirst electrical contact 11 to the p-type substrate 10, a secondelectrical contact 21 to the n-well 20, and a dielectric layer 40.

Next a backside thinning step is performed as well as a backside surfacetreatment, in case of a hybrid imager followed by integration with theROIC. The backside thinning step comprises thinning the substrate 10from the back side 2 to a predetermined final substrate thickness. Inthe example shown in FIG. 2F the plurality of trenches 30 extendsthrough the thinned substrate. However, the present disclosure is notlimited thereto and the trench depth can be smaller than the finalsubstrate thickness.

It is an advantage of some embodiments of the disclosed method thattrenched devices with good quantum efficiency can be made, whilemaintaining the zero cross-talk feature of prior art trenched devices.

A number of experiments were performed in which photodiodes wereprocessed on silicon wafers according to an embodiment of the disclosedmethod. Test diodes suitable for dark current measurements and frontside illuminated measurements were fabricated. In addition, test diodearrays comprising about 1200 pixels connected in parallel werefabricated to evaluate the influence of trenches on the deviceperformance.

In order to better understand the measured values and to evaluate theirsignificance, a number of basic quantum efficiency simulations were madeof representative structures.

FIG. 5 shows the expected (simulated) quantum efficiency for 30micrometer thick backside illuminated imagers in the presence oftrenches in between the pixels. The simulated quantum efficiency isshown both for a perfect trench behavior (i.e., without minority carrierrecombination at the trench sidewalls) (full line, ‘backside normal’),and for a problematic trench behavior (i.e., with substantial minoritycarrier recombination at the trench sidewalls) (dashed line, ‘backsidewith 0.075 microseconds lifetime). It is assumed that the problematictrench behavior as observed in prior art imagers is related to trenchsidewall defects. These defects are simulated by reducing the diffusionlength (decreased lifetime) in the substrate. The trend shown by thesimulations (FIG. 5) is the same as observed for the measurement data(as shown in FIG. 3) of the prior art trenched imagers. In thesimulations, the dielectric parameters were selected to simulate thebackend dielectrics and thus do not represent an optimizedantireflective coating, hence the interference fringes in the simulatedcurves (FIG. 5).

Next, quantum efficiency simulations were performed for front sideillumination, assuming the same device parameters as for the backsidesimulations, and increasing the surface dead zone. The results of thesesimulations for front side illumination are shown in FIG. 6, togetherwith the results for back side illumination. Clearly the differencebetween the two curves for front side illumination (one curve fortrenches with perfect quality (‘normal’) and one curve for trenches withproblematic quality (‘0.075 μs lifetime’)) is substantially smaller thanthe difference between the corresponding curves for the case of backside illumination. The difference in the lower wavelength region betweenthe ‘normal’ (i.e. without minority carrier recombination at the trenchsidewalls) front side illumination curve and the normal back sideillumination curve is due to the surface dead zone which has increased.

Using a measurement setup similar to that schematically shown in FIG. 9,on-wafer measurements were performed and analyzed. The measurement setupcomprises an illuminator 61 with a Xe arc lamp, a ⅛ monochromator 62with motorized filter wheel 63, an optical fiber 64 directing the lightfrom the monochromator to a test sample 65. The test sample is mountedon a moving stage 66, allowing adjusting the optical plane of the testsample or a calibrated reference photodiode 67 with respect to theoptical fiber 64. Accurate positioning of the probe needles on thecontacts of the sample is possible by using micrometer controlled probeheads 68. The system comprising the illuminator and the monochromator isoptimized so that the illuminator output is focused and matched to themonochromator and provides light from 200 nm to 1000 nm with aresolution of 5 nm. The illuminator coupling to the monochromator isfixed by mounting both devices on a common base plate. This mounting kitincludes a light shield to enclose the beam path. The system comprisingthe optical fiber and the moving stage is fixed inside a probe stationwith a metal black cover (dashed line in FIG. 9), providing lightshielding from the environment. Fully automated software proceduresallow fast wavelength scan (70) and accurate multiple point graphacquisition (71).

A rough estimation of the quantum efficiency was obtained by calculatingthe front side fill factor from the design (for the different types oftest diodes) and roughly calibrating the contributions of the guard ringregion (the guard ring not being connected) and the partiallytransparent silicidized regions within the pixels to the simulations. Inother words, these quantum efficiencies are based upon reasonable, yetrough estimations.

FIG. 7 shows the results of quantum efficiency measurements under frontside illumination for test diodes without trenches and for test diodeswith trenches fabricated according to an embodiment of the disclosedmethod. In addition, FIG. 7 shows matching simulations. Although thetest diodes are on the same wafer next to each other, there is a slightdifference between the two measured data sets in the position of thepeaks of the interference fringes. This difference can be explained by avariation in oxide thickness at the front side of about 20 nm (on atotal thickness of about 1460 nm). There is a good agreement between themeasurement results for the non-trenched devices and for the trencheddevices. This indicates that there is no detectable substraterecombination caused by the presence of deep trenches fabricatedaccording to an embodiment of the disclosed method.

FIG. 8 shows the results of quantum efficiency measurements (performedusing the same measurement set-up as for measurements shown in FIG. 7)for test diodes without trenches and for test diodes with trenchesfabricated according to a prior art method. In addition, FIG. 8 showsmatching simulations. While in the lower wavelength range the measureddata sets are substantially the same for the trenched devices and forthe non-trenched devices, towards the NIR (Near Infra Red) the responseof the trenched device appears to be significantly lower than fornon-trenched devices. These data therefore confirm that trenchesfabricated according to prior art methods seem to reduce the minoritycarrier lifetime.

Although measurements are only shown for front side illuminated devices,the good agreement between measurements and simulations (FIG. 7 and FIG.8) provide a good indication that in CMOS imagers fabricated accordingto embodiments of the disclosed method the minority carrier lifetime isnot reduced due to the presence of trenches, as opposed to prior artCMOS imagers with trenches. Therefore, it is expected that the quantumefficiency of back side illuminated CMOS imagers fabricated according toa method of the present disclosure can be substantially better than forprior art back side illuminated CMOS imagers with trenches.

The low quantum efficiency, which limits the performance of prior arttrenched CMOS imagers, was further investigated. The reduced fill factordue to the presence of the trenches accounts only for about 10% of thequantum efficiency loss. The lower quantum efficiency of the prior arttrenched devices could be explained by assuming that recombinationdefects at the surface of the edges (sidewalls) of the trenches aretrapping the charge carriers, thus deteriorating the pixel performance.The wavelength dependency of the diminished quantum efficiency alsopoints into this direction (shorter wavelengths are more affected thanthe longer ones, as can be seen in FIG. 3). If the concentration ofdopants and the potential barrier at the edges of the trenches is toolow to repel the carriers from the surface then this increased surfacerecombination mechanism reduces the quantum efficiency of the device.

To verify this assumption, TSuprem CAD software was used to simulate thediffusion of dopants from the heavily doped polysilicon in the trenchesinto the silicon, in the case of the presence of a thin oxide layer orof trench residues at the edges. The results of these simulations arepresented in FIGS. 4A-B. FIG. 4A shows a schematic cross section of atrench 30 filled with heavily doped polysilicon 32 and with a thinbarrier layer 50 at the trench sidewall. FIG. 4B shows the simulatedeffect of the thickness of the barrier layer 50 on the dopantdistribution profile in the silicon substrate 10, for different barrierlayer thicknesses (0 nm, 1 nm, 2 nm and 5 nm).

This barrier layer can for example be a native oxide, e.g. with athickness of 1 nm to 5 nm, if no proper in-situ cleaning has precededthe filling of the trenches. Using the same thermal annealing parametersas in the actual process flow, different thicknesses of oxide layerswere simulated. As shown in FIG. 4B, the profile of the Boronconcentration resulting from dopant diffusion from the highly dopedpolysilicon is highest and thus the potential barrier at the trenchsidewall is highest in the case where no oxide is present. If the oxidehas a thickness of 1 nm or more, the concentration of dopants in thesilicon at the edge of the trenches is decreased by one, two, or fourorders of magnitude.

The embodiments described provide measures to substantially reduce oravoid the barrier formation in the trenches during processing and thusensure proper diffusion of dopants from the heavily doped polysilicon inthe trenches into the surrounding silicon for fabricating imagers, andmore particularly for fabricating imagers for back side illumination.

1. A method comprising: forming at a front side of a substrate aplurality of high aspect ratio trenches having a predetermined trenchdepth; forming at the front side of the substrate a plurality ofphotodiodes, wherein each photodiode is adjacent at least one trench;forming an oxide layer on inner walls of each trench; removing the oxidelayer; filling each trench with a highly doped material; and thinningthe substrate from a back side opposite the front side to apredetermined final substrate thickness.
 2. The method of claim 1,wherein each trench has a depth at least ten times its width.
 3. Themethod of claim 1, wherein the predetermined trench depth is greaterthan or equal to the predetermined final substrate thickness.
 4. Themethod of claim 1, wherein the highly doped material comprises highlydoped polysilicon.
 5. The method of claim 1, further comprising: formingat least one electrical contact at the front side.
 6. The method ofclaim 1, further comprising: forming a dielectric layer on the firstside.
 7. The method of claim 1, wherein forming each photodiodecomprises: forming a well at the front side; and forming the photodiodeadjacent to the well.
 8. The method of claim 7, wherein each well has aconductivity opposite a conductivity of the substrate.
 9. The method ofclaim 1, wherein forming the oxide layer comprises forming the oxidelayer using at least one of in-situ steam generated oxidation, wetoxidation, dry oxidation, and rapid thermal oxidation.
 10. The method ofclaim 1, further comprising performing a chemical mechanical polishafter filling each trench with the highly doped material.
 11. A methodcomprising: providing a substrate having a predetermined doping profile;forming at a front side of the substrate a plurality of high aspectratio trenches having a predetermined trench depth; forming at the frontside of the substrate a plurality of photodiodes, wherein eachphotodiode is adjacent at least one trench; forming an oxide layer oninner walls of each trench; removing the oxide layer; filling eachtrench with a highly doped material; and thinning the substrate from aback side opposite the front side to a predetermined final substratethickness.
 12. The method of claim 11, wherein the predetermined dopingprofile comprises a graded doping profile.
 13. The method of claim 12,wherein the graded doping profile provides a built-in electric fieldsuitable to guide the flow of photogenerated minority carriers towardsthe front side.
 14. The method of claim 12, wherein the graded dopingprofile comprises one of a continuous slope doping profile and astaircase doping profile.
 15. The method according to claim 11, whereinproviding the substrate comprises: providing a sacrificial substrate;and epitaxially growing a silicon layer with the predetermined dopingprofile on the sacrificial substrate to provide the graded dopingprofile.
 16. The method of claim 11, wherein thinning the substratecomprises removing at least a portion of the sacrificial substrate. 17.A method of fabricating a plurality of complementarymetal-oxide-semiconductor (CMOS) imagers for backside illumination,comprising: forming at a front side of a substrate a plurality of highaspect ratio trenches having a predetermined trench depth; forming atthe front side of the substrate a plurality of photodiodes, wherein eachphotodiode is adjacent at least one trench; forming an oxide layer oninner walls of each trench; removing the oxide layer; filling eachtrench with a highly doped material; and thinning the substrate from aback side opposite the front side to a predetermined final substratethickness.
 18. The method of claim 17, further comprising: performing asurface treatment on the back side.
 19. The method of claim 17, furthercomprising: integrating the CMOS imagers with a readout integratedcircuit.
 20. The method of claim 17, wherein the substrate has apredetermined doping profile.